All Posts by Joël Goossens, PhD

How to avoid interferences in memory accesses on multi-core systems

Commercial off-the-shelf multi-core processors are inescapable nowadays: they are considered to be cheap and powerful. It is common to see processors with four cores or more and several levels of cache in embedded systems (see the figure).

Powerful? It depends. For sure such a platform offers many cores to perform computations simultaneously. But a major issue in critical systems is their lack of predictability. There are a number of bottlenecks, the resources shared between the cores. A typical example is memory accesses. All the cores access the main memory through a shared bus. Concurrency between cores is managed by a hardware bus arbiter that has no awareness of priorities at the level of the application. This causes several types of interferences at run-time.

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