Latency issues are common in embedded software. They are caused by complex, hidden parts
of the software stack. They usually become apparent late in the development process. By nature, they are costly and tricky to fix.
This was not an issue as long as embedded applications remained simple. Most applications were simply not affected by these issues as they were tolerant to latencies in the tens or hundreds of milliseconds. And when latencies mattered, the engineer in charge of the project knew the whole code base and could spend time tweaking timings with precise code optimizations.
This is no longer the case. Modern real-time applications (think machine vision, deep learning) are now entering life-critical embedded systems. They run on powerful multi-core processors and use deep software stacks totaling several millions of lines of code. The specifications require latencies below the millisecond. The complexity at play makes it imperative to use software designed for real-time systems.
Let's analyze what latency is, what are its causes and how we can minimize it.
Commercial off-the-shelf multi-core processors are inescapable nowadays: they are considered to be cheap and powerful. It is common to see processors with four cores or more and several levels of cache in embedded systems (see the figure).
Powerful? It depends. For sure such a platform offers many cores to perform computations simultaneously. But a major issue in critical systems is their lack of predictability. There are a number of bottlenecks, the resources shared between the cores. A typical example is memory accesses. All the cores access the main memory through a shared bus. Concurrency between cores is managed by a hardware bus arbiter that has no awareness of priorities at the level of the application. This causes several types of interferences at run-time.
The EuroCPS consortium has just released the success story related to the development by HIPPEROS of a high-performance multicore mixed-criticality platform for aerospace, robotics and automotive systems. HIPPEROS ported his RTOS on a Thales platform using a Freescale PowerPC multicore board, which Thales uses for safety critical avionics applications, performance benchmarks and isolation characteristics, and implemented a mixed-criticality scheduler with almost perfect performance scaling.
HIPPEROS presented results at the 24th International Conference on Real-Time Networks and Systems (RTNS) in 2016.
We published a paper named “Quantifying Energy Consumption for Practical Fork-Join Parallelism on an Embedded Real-Time Operating System”.
We showed that by using a power-aware parallel programming frameworks for the design of real-time embedded applications, the HIPPEROS RTOS allows system energy savings up to 30% compared to traditional, sequential approaches.
The resulting frameworks are part of the ARIA core.
Nowadays, embedded systems and more generally cyber-physical systems (CPS) are present everywhere in our daily lives. Computers embedded in planes and trains, wearable computing objects and medical devices are only a few examples of such technology-intensive devices in our modern society.