Latency, part one: Why Latency Matters

Latency issues are common in embedded software. They are caused by complex, hidden parts of the software stack. They usually become apparent late in the development process. By nature, they are costly and tricky to fix.

This was not an issue as long as embedded applications remained simple. Most applications were simply not affected by these issues as they were tolerant to latencies in the tens or hundreds of milliseconds. And when latencies mattered, the engineer in charge of the project knew the whole code base and could spend time tweaking timings with precise code optimizations.

This is no longer the case. Modern real-time applications (think machine vision, deep learning) are now entering life-critical embedded systems. They run on powerful multi-core processors and use deep software stacks totaling several millions of lines of code. The specifications require latencies below the millisecond. The complexity at play makes it imperative to use software designed for real-time systems.

Let's analyze what latency is, what are its causes and how we can minimize it.

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Meet us at Hannover Messe 2019

Meet us in Hannover from April 1 to April 5! Modern industrial applications require powerful and reliable software. Come and discover the possibilities offered by the Aria stack and the Maestro RTOS for intelligent autonomous applications. We will demonstrate our latest efforts in simplifying the development of high-performance embedded image processing applications.

Join us in Hall 2, stand C56 with our partners from AWEX.

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How to avoid interferences in memory accesses on multi-core systems

Commercial off-the-shelf multi-core processors are inescapable nowadays: they are considered to be cheap and powerful. It is common to see processors with four cores or more and several levels of cache in embedded systems (see the figure).

Powerful? It depends. For sure such a platform offers many cores to perform computations simultaneously. But a major issue in critical systems is their lack of predictability. There are a number of bottlenecks, the resources shared between the cores. A typical example is memory accesses. All the cores access the main memory through a shared bus. Concurrency between cores is managed by a hardware bus arbiter that has no awareness of priorities at the level of the application. This causes several types of interferences at run-time.

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Successful workshop at HiPEAC 2019

Successful workshop at HiPEAC 2019 for the TULIPP tutorial session! This two-day workshop focused on the benefits of the TULIPP reference platform for vision-based applications.

Our engineers presented the solutions offered by Maestro. For two days, participants had the opportunity to use Maestro to develop an image processing example and then optimize performances by parallelizing their software. They also experimented with hardware acceleration by using the integration with the Xilinx SDSoC toolchain.

We will soon post a version of the tutorial on our website!

More information on the TULIPP project:

Tutorial Session


Meet us in Valencia, Spain from January 21 to January 23! The HiPEAC conference is the premier European forum for experts in computer architecture, programming models, compilers and operating systems for embedded and general-purpose systems.

During this conference we will detail the work accomplished over the course of the TULIPP EU H2020 project. Meet us at the two-day TULIPP tutorial session to discover exciting new features of Maestro, such as the compatibility with the Xilinx SDSoC toolchain.

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Integration of Xilinx SDSoC tools with Maestro

To kick-off the year, we are excited to announce that Maestro is now compatible with the Xilinx SDSoC development environment!

The Maestro SDK now integrates seamlessly with the Xilinx sdscc toolchain and enables automatic hardware acceleration of application code on Xilinx Zynq 7000 and Zynq Ultrascale+ SoCs. This substantially lowers the barrier of entry to accelerate demanding applications using the integrated FPGA. This integration was developed as a part of the TULIPP H2020 EU project.

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Introducing the ARIA Stack

We at HIPPEROS are excited to announce the immediate launch of the ARIA Stack.

The ARIA Stack is a fully integrated combination of a board, RTOS and libraries aimed at making your embedded development for computer vision, robotics and machine learning much faster, easier and efficient.


Success Story for Mixed Criticality Avionics

The EuroCPS consortium has just released the success story related to the development by HIPPEROS of a high-performance multicore mixed-criticality platform for aerospace, robotics and automotive systems. HIPPEROS ported his RTOS on a Thales platform using a Freescale PowerPC multicore board, which Thales uses for safety critical avionics applications, performance benchmarks and isolation characteristics, and implemented a mixed-criticality scheduler with almost perfect performance scaling.

HIPPEROS Technology Showcase at Hannover Messe 2018

​HIPPEROS will be present this year at Hannover Messe on April 25th and 26th in Hall 6 Booth G46 at the stand of the EuroCPS H2020 research project with our partners CEA-LETI, Thales and other members of the project consortium.

HIPPEROS will demonstrate the results of its completed IMICRASAR project to enable efficient mixed criticality applications on multicore platforms, namely a Thales avionics platform and use case. Other HIPPEROS use cases such as high-performance computer vision will also be featured.

Using HIPPEROS middleware is the ideal solution to lower time, cost and effort to create all kinds of smart embedded, high end IoT and edge computing devices.

Take the opportunity to Win a HIPPEROS Development Kit! Come to our stand and take part in the draw to win a complete hardware & software HIPPEROS Development Kit.

EuroCPS H2020

As part of the EuroCPS H2020 initiative to foster innovative European SMEs in the area of CPS, a few selected companies were invited to pitch their project. In this video the HIPPEROS CEO pitches the company mission of Intelligent Autonomy with High Performance Embedded Systems

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